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features ? three input channels for 3d antennas 2.8 mv pp sensitivity typically ultra low current operation consumption 2 a standby current typically 4 a active current typically power supply 2v to 3.8v carrier frequency range from 100 khz to 150 khz wake-up function for a microcontroller header detection baud rate up to 4 kb ps (ask modulation) bi-directional two-wire interface esd according to automotive requirements benefits digital rssi for field strength measurement coils input range from 2.8 mv pp to 2.8v pp typically high sensitivity applications passive entry go (peg)/car access position indicator home access control rfid systems 1. description the ata5282 is a 125-khz ultra low power receiver ic with three input channels for passive entry go applications. it includes a ll circuits for an lf wake-up channel. the three sensitive input stages of the ic amplifier demodulate and measure the input sig- nal from the antenna coils. the microcontroller interface of the ic outputs the data signal as well as the measured rssi values. during standby mode, the header detec- tion unit monitors the incoming signal and generates a wake-up signal for the microcontroller if the ic receives a valid 125-khz carrier signal. by combining the ic with an antenna coil, a microcontroller, an rf transmitter/trans- ceiver and a battery, it is possible to des ign a complete hands-free key for passive entry go applications. ultra low power 125 khz 3d - wake-up receiver with rssi ata5282 4694e?auto?08/05
2 4694e?auto?08/05 ata5282 figure 1-1. block diagram 2. pin configuration figure 2-1. pinning tssop 8l table 2-1. pin description pin symbol function 1 coil1 input: coil channel x 2 coil2 input: coil channel y 3 coil3 input: coil channel z 4 vss circuit ground 5 tc output: current output for oscillator adjustment 6 nscl input: clock for serial interface (default high) 7ndata input/output: i/o data for serial inte rface and field strength measurement/ wake-up function (default high) 8vddbattery voltage ata5282 3 channel amplifier with agc ndata/ nwakeup signal conditioner header detection vdd vss vref battery tc serial interface select field strength nscl 3 8 timing control l2 l1 l3 coil1 coil2 coil3 vss vdd ndata nscl tc 1 2 3 4 8 7 6 5
3 4694e?auto?08/05 ata5282 3. functional description the ata5282 is a 3-channel ask receiver for 125-k hz carrier signals. its three active input stages with very low power consumption and high input sensitivity allow to connect up to 3 antennas for direction-independent wake-up function and data transfer. without a carrier signal the ata5282 operates in standby listen mode. in this mode, it moni- tors the 3 coil inputs with a very low current consumption. to activate the ic and the connected control unit, the transmitting end must send a preamble carrier burst and the header code. when a pream ble has been detected, the ic acti vates the internal oscillator and the header check. the last gap at the end of a valid header enables the ndata output. during data transfer, the ndata pin outputs the demodulated and merged signal of the 3 input stages. to achieve data rates up to 4 kbps for input signals from 2.8 mv pp to 2.8v pp it is necessary to control the gain of the amplifiers. each of the 3 input stages contain an amplifier with auto- matic gain control (agc). it is used to adapt the gain to the incoming signal strength, and is also used as rssi for field strength measurements. the integrated synchronous serial interface uses the nscl together with the ndata pin as clock and data line. it allows to control several functions as well as read out the received signal field strength. enabling only single coil inputs, fr eezing the actual status of the automatic gain control or resetting the complete circuit to the initial state at any time are built-in features. when communication is finished or a time out event occurs, the internal watchdog timer or reset command via the serial interface sets the ic to standby listen mode.
4 4694e?auto?08/05 ata5282 3.1 functional state diagram this diagram gives an overview of the major tasks performed by the ata5282. the detailed function of the automatic gain control that is active during preamble check, header check and data transfer is not shown here. figure 3-1. ata5282 state diagram stand by waiting for rf-signal preamble check signal detected count 192 periods gap detected after 192 periods gap detected before 192 periods check 8 edges of demodulated signal no valid header within 2 ms wake up micro- controller 360 ms watchdog 20 ms quietness check header timeout stop if header ok header ok oscillator run start header check start header timeout check start quietness check start watchdog switch demodulated signal to data output enable data output restart if signal detected no data received for 20 ms 360 ms gone header timing check
5 4694e?auto?08/05 ata5282 3.2 agc amplifier each of the three input stages contain an agc amplifier to amplify the input signal from the coil. the gain is adjusted by the automatic gain control circuit if a preamble signal is detected. the high dynamic range of the agc amplifier enab les the ic to work with input signals from 2.8 mv pp to 2.8v pp . after the agc settling time has elapsed, the amplifier output delivers a 125-khz signal with an amplitude adjusted for the following evaluation circuits (preamble detection, signal conditioner, wake-up). 3.3 automatic gain control for correct demodulation, the signal conditi oner needs an appropriate internal signal ampli- tude. to control the input signal, the ata5282 has a built-in digital agc for each input channel. this gain control circuit regulates the internal signal amplitude to the reference level (ref2, figure 3-2 on page 6 ). the gain control uses the signal of the input channel with the highest amplitude for the regulation as well as signal for the signal conditioner. during the preamble, each period of the carrier signal decreases the gain if the internal signal exceeds the reference level. if the signal does not achieve the reference level, each period increases the gain. after 192 preamble periods, the standard gain control mode is activated. in this mode, the gain is decreased every two peri ods if the internal signal exceeds the reference level and increased every eight periods if the re ference level is not ac hieved. these measures assure that the input signal?s env elope deformation will be minimized. during the gaps between signal bursts, the gain control is frozen to avoid that the gain be modified by noise signals. the tuning range of the agc is subdivided into 256 regulator steps. the settling time for the full tuning range requires 320 periods (192 + (2 64) periods) during a preamble phase. in standby listen mode, the gain is reset to the maximum value. a proper carrier signal acti- vates the automatic gain control. the preamble ( figure 3-7 on page 10 ) with up to 320 periods of the 125 khz magnetic field is used to control the gain of the input amplifiers. to detect the starting point of the header, the start gap should not exceed 256 s (32 periods of 125 khz).
6 4694e?auto?08/05 ata5282 figure 3-2. automatic gain control transmitted signal gain- controlled signal gain control reference gap detection reference 100% 50% ref.1 ref.2 coil input demodulated output
7 4694e?auto?08/05 ata5282 3.4 field strength rssi (recei ved signal strength indicator) the digital value of the agc counter is us ed as an indicator for the corresponding field strength of the input signal. the digital value can be accessed by the microcontroller via the serial interface. figure 3-3. field strength as a function of coil input signal the characteristic gain control value versus the coil input signal (see figure 3-3 ) can be calcu- lated by using the following equation: rssi_v = round (32 ln(v ci ) pp + 190) rssi_v: digital value of field strength ln(): natural logarithm function v ci : coil input voltage with the variation of the gain the coil input impedance changes from high impedance to mini- mal 143 k ? ( figure 3-4 ). this impedance variation is an in significant influence to the quality factor of the resonant circuits. figure 3-4. coil input impedance 0 32 64 96 128 160 192 224 0,001 0,01 0,1 1 10 digital value of field strength (rssi_v) limiter active coil input signal (v ci ) pp 255 max. min. 100 1000 10000 1 10 100 1000 10000 coil input signal (mv pp ) z (k ? ) max. typ. min.
8 4694e?auto?08/05 ata5282 3.5 signal conditioner the signal conditioner operates on the demodulated output signal of all three channels. figure 3-5. function of signal conditioner the agc reduces the gain of all 3 channels with reference to the signal with the highest ampli- tude. this automatically reduces the gain of channels with medium or low input signal amplitudes which results in the suppression of further process of these channels. the logical combination of the 3 demodulated output signals mostly represents the signal with the highest input amplitude. 3.6 preamble detection to prevent the circuit from unintended operations in a noisy environment, the preamble is checked to consist of 192 periods minimum. th ree consecutive periods missing do not disturb counting. with this check passed, the circuit start s the internal oscillator at the end of the pre- amble ( figure 3-9 on page 12 ). the agc needs a maximum of 256 steps for full range tuning of amplifiers. medium signal strength high signal strength low signal strength signal conditioner output (ndata) internal signals input channel 1 internal gap input channel 2 internal gap input channel 3 internal gap
9 4694e?auto?08/05 ata5282 before data transmission occurs the ic remains in standby listen mode. to prevent the circuit from unintended operations in a noisy environment, the preamble detection circuit checks the input signal. a valid signal is detected by a counter circuit after 192 carrier periods without interrupts. short interrupts which are suppressed by the signal conditioner are tolerated. if a valid carrier (preamble) has been found, the circuit starts the automatic gain control. it requires up to 256 carrier periods for settling. the complete preamble should have at least 320 carrier periods. 3.7 internal oscillator if the end of the preamble is detec ted, the internal osc illator starts operating. it works as a time base to generate the time windows for the header detection, the header time-out check, the 20-ms-no-signal check and the data transmission duration watchdog. an external resistor con- nected to tc selects the oscillators freq uency and defines all internal timings. 3.8 header detection and wake-up the preamble needs to be followed by the specific header. this header ensures that the built- in header detection wakes up the controller only with a valid signal. one possible protocol used for wake-up and data transmission is shown in figure 3-7 on page 10 and figure 3-9 on page 12 . the standard header information must be transferred in ook-mode (on-off-keying) with a duty cycle of 50%. the header detection starts with the start gap. a valid header requires 8 consecutive samples of rising and falling edges before the ndata pin switches from high to low. figure 3-6. standard header if no valid header has been detected within 2 ms, beginning at the end of the preamble, the header time-out check stops the oscillator and res ets the gain control as well as the header detection circuit to their initial state. the circuit then waits for the next preamble. standard header 16 periods of 125 khz 16 periods on 1152 s end of preamble demodulated internal signal internal detection windows t start_l t end_l t off t on 16 periods off t start_s t end_s t start_s t end_s t start_s t end_s 32 periods of 125 khz
10 4694e?auto?08/05 ata5282 in case of corrupted data or in a noisy environment, the controller also may use the serial interface to reset the ata5282 to the initial state. this is performed by shifting a specific com- mand into the internal command register. figure 3-7. wake-up protocol for 125-khz ask modulation 320 periods of 125 khz about 2.5 ms about 1 ms internally demodulated signal internal wake-up ndata/ nwakeup header detection 0.5 ms n bit data 01 input signal input signal synch header preamble end of data 32 periods of 125 khz 1 16 periods off header valid internal wake-up 20 ms no signal ndata/ nwakeup 32 periods off 16 periods on
11 4694e?auto?08/05 ata5282 3.9 data output the wake-up signal enables the data pin that delivers the received and demodulated data stream to the controller. sampling and decoding has to be performed by the controller. an example for data coding is give n in the ?n bit data? field ( figure 3-7 on page 10 ). this kind of modulation requires an indication of the end of data, for example, by a burst that differs from the other transmitted bits. as the circuit does not check the received data (except the header), it is up to the base station which kind of m odulation (pulse distance, manchester, bi-phase...) is used. the data output signal is derived from the internal gap detection. table 3-1 describes how the timing depends on different conditions of the a pplied input signal. the q-factor of the external lc-tank as well as the signal strength infl uence the pulse width of the output signal. figure 3-8. output timing conditions a c d b 50% 100% internal ngap internal comporator output coil input a + b = data delay time t on c + d = data delay time t off table 3-1. typical output timing versus signa l strength at 3.2v supply voltage input signal a, c ( figure 3-8 ) b (periods) d (periods) no q q 14 q 20 no q q 14 q 20 minimum, 2.8 mv pp depends on q-factor 3 to 5 4 to 6 5 to 7 3 to 5 4 to 6 4 to 6 medium, v ci < 2.8v pp 3 to 5 4 to 6 5 to 7 3 to 5 4 to 6 4 to 6 strong, v ci 2.8v pp 3 to 5 3 to 5 3 to 5 3 to 5 4 to 6 4 to 6
12 4694e?auto?08/05 ata5282 3.10 current profile and reset function as long as the ata5282 does not receive and recognize a valid preamble, it stays in a low- current listen mode with the gain control and the header detection reset to their initial state. after the circuit has passed the pr eamble check, the internal o scillator and the watchdog (for a 360 ms interval) starts. this results in an increased current consumption. the target of the dif- ferent reset sources is to reduce the current consumption as fast as possible back to the initial value. this can take place at the end of the header time-out check at the earliest. if no valid header has been detected within 2 ms, the circuit switches back to the initial state. with wake-up activated, three further mechanism are available to control the reset. one under control of the connected microcontroller, one if no signal is received and one unconditional after a fixed time. the controller may shift the softres-command into the internal command register to force the circuit into the reset state. this may be useful if the controller detects that the received data are corrupted. the ata5282 itself permanently checks for incoming signals. an interval of 20 ms (no signal received) also leads to the reset state. if there is no valid signal within 20 ms, for ex ample, in a noisy environment or due to customer protocol requirements, the watchdog forces the circ uit into the reset state after a fixed time of 360 ms at the latest. figure 3-9. current profile and reset timing 360 ms interval 2 ms interval current profile data transmission duration watchdog 2 a 4 a 2 a internal oscillator protocol valid preamble detected valid header detected start gap header preamble n bit data header time out check 20 ms interval unconditional reset reset if no data reset if no header detected 20 ms no data
13 4694e?auto?08/05 ata5282 4. serial interface 4.1 general description the serial interface is an easy-to-handle 8-bit 2-wi re interface. it always operates as a slave. the controller uses the nscl input to shift a command into and data out of the internal shift register. the interface starts working with the first falling edge of nscl. ndata/nwakeup serves as bi-directional data i/o for command input and data output. the rising edge of nscl is used to clock the command into the regi ster of the ata5282, while the falling edge is used to shift out the data. da ta changes are always derived from the falling edge of nscl. two operating modes are implemented. one is the command mode that only requires an 8-bit input and does not prepare a data output. this mode is useful to control different operating modes of the ata5282, as described on the following pages. the second mode is used to read out the current value of the agc-counter that is related to the field strength of the input signal. the read_fs command starts an internal sequence to store the value of the agc into the shift register and switches the data i/o to output mode. after t acc , the controller must deliver another 8 shift clocks to clock out the information. figure 4-1. serial interface nscl b d c f e g h a msb msb command data t acc > 50 s t scl data i/o (ndata)
14 4694e?auto?08/05 ata5282 4.2 command and data register the 8-bit command register is organized as follows: table 4-1. command register msb command lsb function freeze ch_sel 1 ch_sel 2 read_fs soft_res not used not used test mod default value after reset: 00 hex 0 application mode active 1 test mode active x for future use x for future use 0 no effect 1 reset circuit to initial state 0no effect 1 read agc-counter (field strength) 0 0 coil input 1, 2, 3 active 0 1 select coil input 1 (disable 2 and 3) 1 0 select coil input 2 (disable 1 and 3) 1 1 select coil input 3 (disable 1 and 2) 0 automatic gain control (agc) active 1 agc stopped with actual value note: these commands, except freeze- and read_fs, cause a reset of agc to initial state. table 4-2. data register msb data lsb function agc7 agc6 agc5 agc4 agc3 agc2 agc1 agc0 default value ?00?hex note: the content of the data register is updated ever y time a read_fs command is given via the interface.
15 4694e?auto?08/05 ata5282 4.3 command description note: every command except freeze- and read_fs ca uses a reset of the agc to its initial state. between every command should be a delay of 50 s. 4.3.1 test_mod not for customer use, this mode is only used for production tests. 4.3.2 soft_res in addition to the internal hardware reset and watchdog functions, this bit allows the connected microcontroller to switch the circuit into the init ial low-power state. all internal registers includ- ing the serial interface and the gain control counter are reset by this command. 4.3.3 read_fs as long as this bit is kept at 0, the interfac e is in write mode and accepts 8-bit commands only. setting read_fs to 1 enables to read out the digi tal 8-bit value of the gain control counter (rssi), thus requiring two 8-bit accesses. the distance between the two accesses (t acc ) must be > 50 s to allow proper operating and updating of the internal data register. 4.3.4 ch_sel0,1 these two bits define the operation mode of the three channels. after reset, all channels are active. with the ch_sel-bits, one of the three channels can be selected to be active, while the other two are disabled. the gain control is reset to the initial value if these bits are modified and operates only with the selected channel. this feature can be used for three-dimensional field strength measurements or to suppress the influence of noise from disturbing channels. 4.3.5 freeze when set to 1, this bit disables the automatic gain control and maintains the actual value for the gain of the input amplifiers. even when changing the input amplitudes (for example, modu- lation through noise or movement), the gain is kept constant. 4.3.6 example the example shows how to program the circ uit to operate on channel 1 only and to measure the field strength of the coil 1 input signal. figure 4-2 shows the command entry which activates coil 1 input only. the gain control counter is set to zero (h ighest sensitivity) by this command. the information is shifted into the ata5282 with the rising edge of the shift clock. figure 4-2. select coil input 1 command 0 0 1 0 0 0 0 0 msb nscl data i/o (ndata)
16 4694e?auto?08/05 ata5282 figure 4-3 shows the second step, the read-out of the actual field strength of the signal applied to coil 1. when 128 steps have been passed, the gain control is finished and the value can be read out. this is performed by providing the command read _fs with the information of the selected channel. 50 s later, the ata5282 has updated and stored the information into the internal shift register. now the microcontroller can read the actual information by generating the next 8 shift clock pulses. the information changes on the falling edge of the clock pulse. figure 4-3. read field strength of channel 1 4.4 reset interface to prevent the system from hanging or running into a deadlock condition due to disturbances on the nscl line (hardware or software), a special function is provided to reset, the interface. figure 4-4. reset interface setting the nscl to a low level and generating 4 clock pulses at the ndata pin resets all interface-relevant registers and flip-flops, thus cancelling the deadlock condition and resyn- chronizing the interface. read command 0 1 1 1 0 0 0 0 msb msb read field strength of coil 1 input signal field strength data nscl > 50 s internal operation data i/o (ndata) down-link up-link nscl reset interface data i/o (ndata)
17 4694e?auto?08/05 ata5282 5. application figure 5-1 shows an application of the ata5282. combined with the antenna resonant circuit, the ata5282 is used as wake-up receiver for the microcontroller. additional to the antenna cir- cuits the blocking filter - consisting of a rc element (r 1 = 100 ? , c 1 = 4.7 f) - is necessary for the ata5282. an additional resistor (r 2 = 2 m ? /1%) should be placed at tc for oscillator tun- ing (optional: a parallel capacitor c 2 with maximum 10 pf). figure 5-1. application circuit note: unused channels should be connected to v dd . timing serial interace header detect ata5282 vdd z y x uhf receiver ata5743 433 mhz 125 khz antenna driver ata5278 central board controller c 1 micro- controller marc4 uhf module ata5757 r 1 r 2 c 2 tc ndata nscl gnd
18 4694e?auto?08/05 ata5282 figure 5-2. pin connection and pin protection coil1 coil2 coil3 vdd ndata nscl tc vss vdd vdd ata5282 1 2 3 4 8 7 6 5 divider impedance 143 k ? to 5 m ? divider impedance 143 k ? to 5 m ? divider impedance 143 k ? to 5 m ? 18 k ? 1 k ? 1 k ? 2 k ? 20 k ? vdd
19 4694e?auto?08/05 ata5282 6. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol value unit power supply v dd ?0.3 to +6.5 v input voltage (except coil inputs) v in v ss ? 0.3 < v in < v dd + 0.3 v input current coil i ci 10 ma input voltage coil v ci v dd ? 3.5 < v ci < v dd + 3.5 v esd protection (human body) v esd 4kv operating temperature range t amb ?40 to +85 c storage temperature range t stg ?40 to +130 c soldering temperature t sld 260 c 7. thermal resistance parameters symbol value unit thermal resistance junction-case r thjc 260 k/w thermal resistance junction-ambient r thja 240 k/w 8. operating range parameters symbol value unit power supply range v dd 2 to 3.8 v operating temperature range t op ?40 to +85 c
20 4694e?auto?08/05 ata5282 9. electrical characteristics v ss = 0v, v dd = 0v to 3.8v, t amb = ?40c to 85c unless otherwise specified no. parameters test conditions pin symbol min. typ. max. unit type* 1 power supply and coil limiter 1.1 power supply 8 v dd 23.23.8va 1.2 supply current (initial state, agc off) 8i dd 24aa 1.3 supply current (agc active) 8 i dd 46aa 1.4 power on reset threshold v por 11.51.9va 1.5 power up time switch on v dd to circuit active v pon 100 ms c 1.6 reset reactivation caused by negative spikes on v dd t bdn = 500 ns 7 t rst 10 100 s c 1.71 1.72 1.73 coil input voltage referred to v dd (input coil limiter for channels x, y, z) i ci = 1 ma v dd = 2.0v v dd = 3.2v v dd = 3.8v 1, 2, 3 v ci 1.2 1.4 1.55 v p v p v p a 1.8 tc low current output v o_tc at 500 mv 5 i tc 205 250 280 na a 1.9 carrier frequency range 1, 2, 3 f cf 100 150 khz d 2 amplifiers 2.1 wake-up sensitivity 125-khz input signal 7 v sens 2.8 4.9 mv pp a 2.2 bandwidth without coil b w 150 khz c 2.3 upper corner frequency without coil f u 180 khz c 2.4 lower corner frequency without coil f o 30 khz c 2.5 gain difference maximum/minimum value (decimal) of channels rssi_vmax ? rssi_vmin (see figure 3-3 on page 7 ) 1, 2, 3 g diff 16 a 2.6 input impedance v in 2.8 mv pp at 125 khz 1, 2, 3 r in 143 k ? a 2.7 input capacitance 1, 2, 3 c in 10 pf c 2.8 coils input range v ci = 2.8 mv pp v ci = 2.8 v pp 1, 2, 3 60 db a 3 digital 3.1 oscillator frequency r ext = 2 m ? and c ext maximum 10 pf f osc 80 90 100 khz a 3.2 preamble periods v ci 1v pp 1, 2, 3 n pa m 320 a 3.3 header detection windows (l = long, s = short) see figure 3-6 on page 9 tolerance included oscillator tolerance t start_l 160 182 205 s d 3.4 t end_l 315 357 400 s d 3.5 t start_s 40 50 60 s a 3.6 t end_s 200 225 255 s d 3.7 shift clock period 6 t nscl 10 s c 3.8 data access time t acc 50 s a 3.9 data rate (q < 20) 125 khz ask d rate 4kbpsa 3.10 delay time rf signal to data 125 khz ask t on 40 s a 3.11 delay time rf signal to data 125 khz ask t off 40 s a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
21 4694e?auto?08/05 ata5282 4 interface 4.1 nscl input level low 6 v il_nscl v ss 0.2 v dd va 4.2 nscl input level high 6 v ih_nscl 0.8 v dd v dd va 4.3 nscl input leakage current low v nscl = v ss 6i il_nscl ?200 0 na a 4.4 nscl input leakage current high v nscl = v dd 6i ih_nscl 0+200naa 4.5 ndata input level low v nscl = v ss 7v il_ndat v ss 0.2 v dd va 4.6 ndata input level high v nscl = v ss 7v ih_ndat 0.8 v dd v dd va 4.7 ndata input leakage current low v ndat = v ss v nscl = v ss 7i il_ndat ?200 0 na a 4.8 ndata input leakage current high v ndat = v dd v nscl = v ss 7i ih_ndat 0+200naa 4.9 ndata output level low i ndat = +70 a v nscl = v dd 7v ol_ndat v ss 0.2 v dd va 4.10 ndata output level high i ndat = ?70 a v nscl = v dd 7v ol_ndat 0.8 v dd v dd va 9. electrical characteristics (continued) v ss = 0v, v dd = 0v to 3.8v, t amb = ?40c to 85c unless otherwise specified no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
22 4694e?auto?08/05 ata5282 11. package information figure 11-1. package tssop 8l 10. ordering information extended type number package remarks ata5282-6aqh tssop 8l 5000 pcs taped and reeled, pb-free ata5282-6aph tssop 8l 500 pcs taped and reeled, pb-free
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